News

Design And Reuse6h
Creonic Adds oFEC Codec IP Core to Portfolio, Expanding High-Speed Networking Solutions for ASIC and FPGA
Creonic GmbH, a leading provider of ready-to-use IP cores for ASIC and FPGA applications, announces the release of its new oFEC (Open Forward Error Correction) codec IP core. The solution supports ...
Design And Reuse12h
Expedera s Origin Evolution NPU IP Brings Generative AI to Edge Devices
Expedera launches its Origin Evolution NPU IP, bringing hardware acceleration to meet the computational demands of running ...
Design And Reuse14h
PolarFire Core devices streamline costs while retaining the market-leading power efficiency, security and reliability of classic PolarFire families
PolarFire Core devices are supported by Microchip’s Libero® SoC Design Suite, SmartHLS™ compiler, VectorBlox™ Accelerator SDK and Microchip’s Mi-V ecosystem of partner platforms for rapid RISC-V ...
Design And Reuse14h
Boosting RISC-V SoC performance for AI and ML applications
At around the same time, the open and configurable RISC-V instruction set architecture (ISA) is experiencing rapid adoption across diverse markets. This growth aligns with rising SoC complexity and ...
Design And Reuse14h
BrainChip CTO to Present on Architectural Innovation for Low-Power AI at the Embedded Vision Summit
Attendees of the Summit can visit BrainChip at booth #716 to see live demonstrations of the company’s latest advancements in Edge AI technology, including innovations in on-chip language processing, ...
Design And Reuse1d
sureCore extends its sureFIT design service to include custom memory solutions for AI applications
Sheffield, UK – 20 May 2025. SureCore, the leading memory specialist, has announced the expansion of its sureFIT design service to include AI applications, using its memory design expertise to help AI ...
Design And Reuse1d
NVIDIA Unveils NVLink Fusion for Industry to Build Semi-Custom AI Infrastructure With NVIDIA Partner Ecosystem
COMPUTEX - May 19, 2025 — NVIDIA today unveiled NVIDIA NVLink Fusion™ — new silicon that lets industries build semi-custom AI infrastructure with the vast ecosystem of partners building with NVIDIA ...
Design-Reuse2d
Low Power PCIe3 SERDES PHY - TSMC 40G
Analog Bits Programmable SERDES provides a Physical Media Attachment (PMA) Layer capable of signaling at multiple data rates and supports multi-protocol market needs including a wide range of ac- ...
Design-Reuse2d
Worldwide Silicon Wafer Shipments and Revenue Fall in 2023, SEMI Reports
MILPITAS, Calif. — February 7, 2024 — Worldwide silicon wafer shipments in 2023 decreased 14.3% to 12,602 million square inches while wafer revenue contracted 10.9% to $12.3 billion over the same ...
Design-Reuse2d
MIPI C-PHY TRx 2.5Gsps / D-PHY TRx 4.5Gbps Combo PHY (5nm)
The MIPI D-PHY/C-PHY Combo IP supports data rates of up to 4.5Gbps for D-PHY and 2.5Gsps for C-PHY. It operates in High-Speed (HS), Low-Power (LP), and Escape modes, where High-Speed mode provides ...
Design-Reuse2d
300mm Fab Equipment Spending Forecast to Reach Record $137 Billion in 2027, SEMI Reports
MILPITAS, Calif. — March 20, 2024 — Global 300mm fab equipment spending for front-end facilities is forecast to reach a record US$137 billion in 2027 after topping US$100 billion for the first time by ...
Design-Reuse2d
CCSDS 131.2 SCCC Turbo Encoder and 64-APSK Modulator
The IPrium-CCSDS-SCCC-Modulator-Encoder IP Core implements the CCSDS modulation standard 131.2-B. The IP Core is a complete digital QPSK, 8-PSK, 16-APSK, 32-APSK and 64-APSK modulator with an ...